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connection diagram 8-pin plastic mini-dip (n), cerdip (q) and soic (r) packages x1 x2 y1 y2 v p out nc v n AD830 nc = no connect 1 2 3 4 8 7 6 5 a=1 v ? 1 v ? 1 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a high speed, video difference amplifier AD830 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features differential amplification wide common-mode voltage range: +12.8 v, C12 v differential voltage range: 6 2 v high cmrr: 60 db @ 4 mhz built-in differential clipping level: 6 2.3 v fast dynamic performance 85 mhz unity gain bandwidth 35 ns settling time to 0.1% 360 v/ m s slew rate symmetrical dynamic response excellent video specifications differential gain error: 0.06% differential phase error: 0.08 8 15 mhz (0.1 db) bandwidth flexible operation high output drive of 6 50 ma min specified with both 6 5 v and 6 15 v supplies low distortion: thd = C72 db @ 4 mhz excellent dc performance: 3 mv max input offset voltage applications differential line receiver high speed level shifter high speed in-amp differential to single ended conversion resistorless summation and subtraction high speed a/d driver product description the AD830 is a wideband, differencing amplifier designed for use at video frequencies but also useful in many other applica- tions. it accurately amplifies a fully differential signal at the frequency ?hz cmrr ?db 110 30 10m 50 40 1k 70 60 80 90 100 1m 100k 10k v s = 15v v s = 5v common-mode rejection ratio vs. frequency input and produces an output voltage referred to a user-chosen level. the undesired common-mode signal is rejected, even at high frequencies. high impedance inputs ease interfacing to fi- nite source impedances and thus preserve the excellent common-mode rejection. in many respects, it offers significant improvements over discrete difference amplifier approaches, in particular in high frequency common-mode rejection. the wide common-mode and differential-voltage range of the AD830 make it particularly useful and flexible in level shifting applications, but at lower power dissipation than discrete solu- tions. low distortion is preserved over the many possible differ- ential and common-mode voltages at the input and output. good gain flatness and excellent differential gain of 0.06% and phase of 0.08 make the AD830 suitable for many video system applications. furthermore, the AD830 is suited for general pur- pose signal processing from dc to 10 mhz. 9 ? ?1 100k 1g 10m 1m 10k ? 0 3 6 ?8 ?5 ?2 ? frequency ?hz gain ?db 100m v s = 5v r l = 150 w c l = 4.7pf c l = 15pf c l = 33pf closed-loop gain vs. frequency, gain = +1
rev. a C2C AD830Cspecifications (v s = 6 15 v, r load = 150 v , c load = 5 pf, t a = +25 8 c unless otherwise noted) AD830j/a AD830s 1 parameter conditions min typ max min typ max units dynamic characteristics 3 db small signal bandwidth gain = 1, v out = 100 mv rms 75 85 75 85 mhz 0.1 db gain flatness frequency gain = 1, v out = 100 mv rms 11 15 11 15 mhz differential gain error 0 to +0.7 v, frequency = 4.5 mhz 0.06 0.09 0.06 0.09 % differential phase error 0 to +0.7 v, frequency = 4.5 mhz 0.08 0.12 0.08 0.12 degrees slew rate 2 v step, r l = 500 w 360 360 v/ m s 4 v step, r l = 500 w 350 350 v/ m s 3 db large signal bandwidth gain = 1, v out = 1 v rms 38 45 38 45 mhz settling time, gain = 1 v out = 2 v step, to 0.1% 25 25 ns v out = 4 v step, to 0.1% 35 35 ns harmonic distortion 2 v p-p, frequency = 1 mhz C82 C82 dbc 2 v p-p, frequency = 4 mhz C72 C72 dbc input voltage noise frequency = 10 khz 27 27 nv/ ? hz input current noise 1.4 1.4 pa/ ? hz dc performance offset voltage gain = 1 1.5 3 1.5 3mv gain = 1, t min Ct max 5 7mv open loop gain dc 64 69 64 69 db gain error r l = 1 k w , g = 1 0.1 0.6 0.1 0.6 % peak nonlinearity, r l = 1 k w , C1 v x +1 v 0.01 0.03 0.01 0.03 % fs gain = 1 C1.5 v x +1.5 v 0.035 0.07 0.035 0.07 % fs C2 v x +2 v 0.15 0.4 0.15 0.4 % fs input bias current v in = 0 v, +25 c to t max 510 510 m a v in = 0 v, t min 713 817 m a input offset current v in = 0 v, t min Ct max 0.1 1 0.1 1 m a input characteristics differential voltage range v cm = 0 2.0 2.0 v differential clipping level 2 pins 1 and 2 inputs only 2.1 2.3 2.1 2.3 v common-mode voltage range v dm = 1 v C12.0 +12.8 C12.0 +12.8 v cmrr dc, pins 1, 2, 10 v 90 100 90 100 db dc, pins 1, 2, 10 v, t min Ct max 88 86 db frequency = 4 mhz 55 60 55 60 db input resistance 370 370 k w input capacitance 2 2 pf output characteristics output voltage swing r l 3 1 k w 12 +13.8, C13.8 12 +13.8, C13.8 v r l 3 1 k w , 16.5 v s 13 +15.3, C14.7 13 +15.3, C14.7 v short circuit current short to ground 80 80 ma output current r l = 150 w 50 50 ma power supplies operating range 4 16.5 4 16.5 v quiescent current t min Ct max 14.5 17 14.5 17 ma + psrr (to v p ) dc, g = 1 86 86 db C psrr (to v n ) dc, g = 1 68 68 db psrr dc, g = 1, 5 to 15 v s 66 71 66 71 db psrr dc, g = 1, 5 to 15 v s , t min Ct max 62 68 60 68 db notes 1 see standard military drawing 5962-9313001mpa for specifications. 2 clipping level function on x channel only. specifications subject to change without notice.
AD830 rev. a C3C (v s = 6 5 v, r load = 150 v , c load = 5 pf, t a = +25 8 c unless otherwise noted) AD830j/a AD830s 1 parameter conditions min typ max min typ max units dynamic characteristics 3 db small signal bandwidth gain = 1, v out = 100 mv rms 35 40 35 40 mhz 0.1 db gain flatness frequency gain = 1, v out = 100 mv rms 5 6.5 5 6.5 mhz differential gain error 0 to +0.7 v, frequency = 4.5 mhz, g = +2 0.14 0.18 0.14 0.18 % differential phase error 0 to +0.7 v, frequency = 4.5 mhz, g = +2 0.32 0.4 0.32 0.4 degrees slew rate, gain = 1 2 v step, r l = 500 w 210 210 v/ m s 4 v step, r l = 500 w 240 240 v/ m s 3 db large signal bandwidth gain = 1, v out = 1 v rms 30 36 30 36 mhz settling time v out = 2 v step, to 0.1% 35 35 ns v out = 4 v step, to 0.1% 48 48 ns harmonic distortion 2 v p-p, frequency = 1 mhz C69 C69 dbc 2 v p-p, frequency = 4 mhz C56 C56 dbc input voltage noise frequency = 10 khz 27 27 nv/ ? hz input current noise 1.4 1.4 pa/ ? hz dc performance offset voltage gain = 1 1.5 3 1.5 3mv gain = 1, t min Ct max 4 5mv open loop gain dc 60 65 60 65 db unity gain accuracy r l = 1 k w 0.1 0.6 0.1 0.6 % peak nonlinearity, r l = 1 k w C1 v x +1 v 0.01 0.03 0.01 0.03 % fs C1.5 v x +1.5 v 0.045 0.07 0.045 0.07 % fs C2 v x +2 v 0.23 0.4 0.23 0.4 % fs input bias current v in = 0 v, +25 c to t max 510 510 m a v in = 0 v, t min 713 817 m a input offset current v in = 0 v, t min Ct max 0.1 1 0.1 1 m a input characteristics differential voltage range v cm = 0 2.0 2.0 v differential clipping level 2 pins 1 and 2 inputs only 2.0 2.2 2.0 2.2 v common-mode voltage range v dm = 1 v C2.0 +2.9 C2.0 +2.9 v cmrr dc, pins 1, 2, +4 v to C2 v 90 100 90 100 db dc, pins 1, 2, +4 v to C2 v, t min Ct max 88 86 db frequency = 4 mhz 55 60 55 60 db input resistance 370 370 k w input capacitance 2 2 pf output characteristics output voltage swing r l 3 150 w 3.2 3.5 3.2 3.5 v r l 3 150 w , 4 v s 2.2 +2.7, C2.4 2.2 +2.7, C2.4 v short circuit current short to ground C55, +70 C55, +70 ma output current 40 40 ma power supplies operating range 4 16.5 4 16.5 v quiescent current t min Ct max 13.5 16 13.5 16 ma + psrr (to v p ) dc, g = 1, offset 86 86 db C psrr (to v n ) dc, g = 1, offset 68 68 db psrr (dual supply) dc, g = 1, 5 to 15 v s 66 71 66 71 db psrr (dual supply) dc, g = 1, 5 to 15 v s , t min Ct max 62 68 60 68 db notes 1 see standard military drawing 5962-9313001mpa for specifications. 2 clipping level function on x channel only. specifications subject to change without notice.
AD830 rev. a C4C absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation 2 . . . . . . . observe derating curves output short circuit duration . . . . observe derating curves common-mode input voltage . . . . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . v s storage temperature range (q) . . . . . . . . . C65 c to +150 c storage temperature range (n) . . . . . . . . . C65 c to +125 c storage temperature range (r) . . . . . . . . . C65 c to +125 c operating temperature range AD830j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 c to +70 c AD830a . . . . . . . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c AD830s . . . . . . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c lead temperature range (soldering 60 seconds) . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 8-pin plastic package: q ja = 90 c/watt 8-pin soic package: q ja = 155 c/watt 8-pin cerdip package: q ja = 110 c/watt maximum power dissipation the maximum power that can be safely dissipated by the AD830 is limited by the associated rise in junction temperature. for the plastic packages, the maximum safe junction tempera- ture is 145 c. for the cerdip, the maximum junction tempera- ture is 175 c. if these maximums are exceeded momentarily, proper circuit operation will be restored as soon as the die tem- perature is reduced. leaving the AD830 in the overheated condition for an extended period can result in permanent dam- age to the device. to ensure proper operation, it is important to observe the recommended derating curves. while the AD830 output is internally short circuit protected, this may not be sufficient to guarantee that the maximum junc- tion temperature is not exceeded under all conditions. if the output is shorted to a supply rail for an extended period, then the amplifier may be permanently destroyed. esd susceptibility esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 volts, which readily accumulate on the human body and on test equipment, can discharge without de- tection. although the AD830 features proprietary esd protec- tion circuitry, permanent damage may still occur on these devices if they are subjected to high energy electrostatic dis- charges. therefore, proper esd precautions are recommended to avoid any performance degradation or loss of functionality. ordering guide model temperature range package description package option AD830an C40 c to +85 c 8-pin plastic mini-dip n-8 AD830jr 0 c to +70 c 8-pin soic r-8 5962-9313001mpa* C55 c to +125 c 8-pin cerdip q-8 *see standard military drawing for specifications. 2.5 0 90 1.5 0.5 ?0 1.0 ?0 2.0 70 50 30 10 ?0 ambient temperature c total power dissipation ?watts t j max = 145 c 8-pin mini-dip 8-pin soic maximum power dissipation vs. temperature, mini-dlp and soic packages 3.0 0.2 140 0.8 0.4 ?0 0.6 ?0 1.4 1.0 1.2 1.6 2.0 2.2 2.8 2.4 1.8 100 120 80 60 40 20 0 ?0 ambient temperature ? c total power dissipation ?watts t j max = 175 c 8-pin cerdip maximum power dissipation vs. temperature, cerdip package
AD830 rev. a C5C frequency ?hz cmrr ?db 110 30 10m 50 40 1k 70 60 80 90 100 1m 100k 10k v s = 15v v s = 5v figure 1. common-mode rejection ratio vs. frequency frequency ?hz ?0 ?0 ?0 10k 10m 1m 100k 1k ?0 ?0 harmonic distortion ?dbc v out = 2v p-p r l = 150 w gain = +1 5v supplies 2nd harmonic 3rd harmonic 15v supplies 2nd harmonic 3rd harmonic figure 2. harmonic distortion vs. frequency junction temperature ? c input current ? m a 9 3 140 6 4 ?0 5 ?0 8 7 120 80 60 40 100 20 0 ?0 figure 3. input bias current vs. temperature typical characteristicsC frequency ?hz psrr ?db 100 10 10m 30 20 1k 40 50 60 70 80 90 1m 100k 10k to v p @ 15v to v p @ 5v to v n @ 15v to v n @ 5v figure 4. power supply rejection ratio vs. frequency frequency ?hz 3 ?2 ?7 100k 100m 10m 1m 10k ? ? ? 0 ?4 ?1 ?8 ?5 gain ?db 15v 5v 1g 10v r l = 150 w c l = 4.7pf figure 5. closed-loop gain vs. frequency g = +1 junction temperature ? c input offset voltage ?mv 3 ? 140 ? ? ?0 ? ?0 2 0 1 120 100 80 60 40 20 0 ?0 5v s 15v s 10v s figure 6. input offset voltage vs. temperature
AD830 rev. a C6C 0.10 0.03 0.01 0.02 0.06 0.04 0.05 0.07 0.08 0.09 15 6 5 0.10 0.03 0.01 0.02 0.06 0.04 0.05 0.07 0.08 0.09 14 13 12 11 10 9 8 7 supply voltage ? volts differential gain ?% differential phase ?degrees phase gain gain = +2 r l = 500 w freq = 4.5mhz figure 7. differential gain and phase vs. supply voltage, r l = 500 w ?0 ?00 2.00 ?0 ?0 0.50 ?0 0.25 ?0 ?0 1.75 1.25 1.00 0.75 1.50 peak amplitude ?volts harmonic distortion ?db hd3 ( 15v) 100khz hd2 ( 5v) 100khz hd2 ( 15v) 100khz hd3 ( 5v) 100khz figure 8. harmonic distortion vs. peak amplitude, frequency = 100 khz 50 10 100 10m 40 20 1k 30 100k 1m 10k frequency ?hz input voltage noise ?nv/ ? hz figure 9. noise spectral density 0.20 15 0.06 0.02 6 0.04 5 0.12 0.08 0.10 0.14 0.16 0.18 14 13 12 11 10 9 8 7 supply voltage ? volts differential gain ?% differential phase ?degrees gain phase 0.40 0.12 0.04 0.08 0.24 0.16 0.20 0.28 0.32 0.36 gain = +2 r l = 150 w freq = 4.5mhz figure 10. differential gain and phase vs. supply voltage, r l = 150 w ?0 ?00 2.00 ?0 ?0 0.50 ?0 0.25 ?0 ?0 1.75 1.25 1.00 0.75 1.50 peak amplitude ?volts harmonic distortion ?db hd2 ( 15v) 4mhz hd3 ( 15v) 4mhz hd2 ( 5v) 4mhz hd3 ( 5v) 4mhz figure 11. harmonic distortion vs. peak amplitude, frequency = 4 mhz junction temperature ? c quiescent supply current?ma 15.00 12.25 140 13.00 12.50 ?0 12.75 ?0 13.75 13.25 13.50 14.00 14.25 14.50 14.75 120 100 80 60 40 20 0 ?0 16.5v s 5v s figure 12. supply current vs. junction temperature
AD830 rev. a C7C typical characteristicsC 3 ?2 ?7 1m 1g 100m 10m 100k ? ? ? 0 ?4 ?1 ?8 ?5 frequency ?hz unity gain connection gain of 2 connection 9 ? ?1 ? 0 3 6 ?8 ?5 ?2 ? 15v 5v r l = 150 w c l = 0pf figure 13. closed-loop gain vs. frequency for the three common connections of figure 16 10 90 100 0% 100mv 20 ns v s = 15v v s = 5v figure 14. small signal pulse response, r l = 150 w , c l = 4.7 pf, g = +1 9 ? ?1 100k 1g 10m 1m 10k ? 0 3 6 ?8 ?5 ?2 ? frequency ?hz gain ?db 100m v s = 5v r l = 150 w c l = 4.7pf c l = 15pf c l = 33pf figure 15. closed-loop gain vs. frequency vs. c l , g = +1. v s = 5 v v 1 v p out v n v out = 2v 1 resistor less gain of 2 1 2 4 3 8 7 5 6 AD830 c a=1 g m g m v out = v 1 gain of 1 v 1 v p out v n 1 2 4 3 8 7 5 6 AD830 c a=1 g m g m v out = v 1 op-amp connection v 1 v p out v n 1 2 4 3 8 7 5 6 AD830 c a=1 g m g m (a) (b) (c) figure 16. connection diagrams 10 90 100 0% 1v 20 ns v s = 15v v s = 5v figure 17. large signal pulse response, r l = 150 w , c l = 4.7 pf, g = +1 9 ? ?1 100k 100m 10m 1m 10k ? 0 3 6 ?8 ?5 ?2 ? frequency ?hz gain ?db v s = +15v r l = 150 w c l = 4.7pf c l = 15pf c l = 33pf 1g figure 18. closed-loop gain vs. frequency, vs. c l , g = +1. v s = 15 v
AD830 rev. a C8C traditional differential amplification in the past, when differential amplification was needed to reject common-mode signals superimposed with a desired signal; most often the solution used was the classic op amp based difference amplifier shown in figure 19. the basic function v o = v 1 Cv 2 is simply achieved, but the overall performance is poor and the cir- cuit possesses many serious problems that make it difficult to re- alize a robust design with moderate to high levels of performance. r 1 r 2 r 3 r 4 v out v 2 v 1 only if r 1 = r 2 = r 3 = r 4 does v out = v 1 ?v 2 figure 19. op amp based difference amplifier problems with the op amp based approach ? low common-mode rejection ratio (cmrr) ? low impedance inputs ? cmrr highly sensitive to the value of source r ? different input impedance for the + and C input ? poor high frequency cmrr ? requires very highly matched resistors r 1 Cr 4 to achieve high cmrr ? halves the bandwidth of the op amp ? high power dissipation in the resistors for large common- mode voltage AD830 for differential amplification the AD830 amplifier was specifically developed to solve the listed problems with the discrete difference amplifier approach. its topology, discussed in detail in a later section, by design acts as a difference amplifier. the circuit of figure 20 shows how simply the AD830 is configured to produce the difference of two signals v 1 and v 2 , in which the applied differential signal is exactly reproduced at the output relative to a separate output common. any common-mode voltage present at the input is removed by the AD830. a=1 v ? i v ? i v out v 2 v 1 v out = v 1 ?v 2 i y i x figure 20. AD830 as a difference amplifier advantageous properties of the AD830 ? high common-mode rejection ratio (cmrr) ? high impedance inputs ? symmetrical dynamic response for +1 and C1 gain ? low sensitivity to the value of source r ? equal input impedance for the + and C input ? excellent high frequency cmrr ? no halving of the bandwidth ? constant power distortion vs. common-mode voltage ? highly matched resistors not needed
AD830 rev. a C9C understanding the AD830 topology the AD830 represents analog devices first amplifier product to embody a powerful alternative amplifier topology. referred to as active feedback, the topology used in the AD830 provides in- herent advantages in the handling of differential signals, differ- ing system commons, level shifting and low distortion, high frequency amplification. in addition, it makes possible the implementation of many functions not realizable with single op amp circuits or is superior to op amp based equivalent circuits. with this in mind, it is important to understand the internal structure of the AD830. the topology, reduced to its elemental form, is shown below in figure 21. nonideal effects such as nonlinearity, bias currents and limited full scale are omitted from this model for simplicity, but are discussed later. the key feature of this topology is the use of two, identical voltage-to-current converters, g m , that make up input and feedback signal interfaces. they are labeled with inputs v x and v y , respectively. these voltage to current converters possess fully differential inputs, high linearity, high input impedance and wide voltage range operation. this enables the part to handle large amplitude differential signals; they also provide high common-mode rejection, low distortion and negli- gible loading on the source. the label, g m , is meant to convey that the transconductance is a large signal quantity, unlike in the front-end of most op amps. the two g m stage current outputs i x and i y , sum together at a high impedance node which is char- acterized by an equivalent resistance and capacitance connected to an ac common. a unity voltage gain stage follows the high impedance node to provide buffering from loads. relative to either input, the open loop gain, a ol , is set by the transconductance, g m , working into the resistance, r p ; a ol = g m 3 r p . the unity gain frequency w 0 db for the open loop gain is established by the transconductance, g m , working into the capacitance, c c ; w 0 db = g m /c c . the open loop description of the AD830 is shown below for completeness. a=1 v out v x2 v x1 i x = (v x1 ?v x2 ) g m i y = (v y1 ?v y2 ) g m i z = i x + i y i y i x v y2 v y1 g m g m i z a ols = g m r p 1 + s (c c r p ) c c r p figure 21. topology diagram a=1 v out v x2 v x1 v x1 ?v x2 = v y 2 ?v y1 for v y2 = v out v out = (v x1 ?v x2 + v y1 ) i y i x v y2 v y1 g m g m 1 1 + s(c c /g m ) c c figure 22. closed-loop connection precise amplification is accomplished through closed-loop op- eration of this topology. voltage feedback is implemented via the y g m stage in which where the output is connected to the Cy input for negative feedback as shown in figure 22. an input signal is applied across the x g m stage, either fully differentially or single-ended referred to common. it produces a current sig- nal which is summed at the high impedance node with the out- put current from the y g m stage. negative feedback nulls this sum to a small error current necessary to develop the output voltage at the high impedance node. the error current is usually negligible, so the null condition essentially forces the y g m output stage current to exactly equal the x g m output current. since the two transconductances are identical, the differential voltage across the y inputs equals the negative of the differential voltage across the x input; v y = Cv x or more precisely v y2 Cv y1 = v x1 Cv x2 . this simple relation provides the basis to easily analyze any function possible to synthesize with the AD830, including any feedback situation. the bandwidth of the circuit is defined by the g m and the capacitor c c . the highly linear g m stages give the amplifier a single pole response, excluding the output amplifier and loading effects. it is important to note that the bandwidth and general dy- namic behavior is symmetrical (identical) for the noninverting and the inverting connections of the AD830. in addition, the input im- pedance and cmrr are the same for either connections. this is very advantageous and unlike in a voltage or current feedback amplifier, where there is a distinct difference in performance be- tween the inverting and noninverting gain. the practical impor- tance of this cannot be overemphasized and is a key feature offered by the AD830 amplifier topology.
AD830 rev. a C10C interfacing the input common-mode voltage range the common-mode range of the AD830 is defined by the am- plitude of the differential input signal and the supply voltage. the general definition of common-mode voltage, v cm , is usu- ally applied to a symmetrical differential signal centered about a particular voltage as illustrated by the diagram in figure 23. this is the meaning implied here for common-mode voltage. the internal circuitry establishes the maximum allowable volt- age on the input or feedback pins for a given supply voltage. this constraint and the differential input voltage sets the common-mode voltage limit. figure 24 shows a curve of the common-mode voltage range vs. differential voltage for three supply voltage settings. v max v peak v cm figure 23. common-mode definition 15 0 2.0 3 0 6 9 12 1.6 1.2 0.8 0.4 +v cm 15v = v s 10v = v s 5v = v s +v cm +v cm ? cm ? cm ? cm differential input voltage ?v peak common-mode voltage ? volts figure 24. input common-mode voltage range vs. differential input voltage differential voltage range the maximum applied differential voltage is limited by the clip- ping range of the input stages. this is nominally set at 2.4 volts magnitude and depicted in the crossplot (x-y) photo of figure 25. the useful linear range of the input stages is set at 2 volts, but is actually a function of the distortion required for a particu- lar application. the distortion increases for larger differential input voltages. a plot of relative distortion versus input differen- tial voltage is shown in figures 8 and 11 in the typical charac- teristics section. the distortion characteristics could impose a secondary limit to the differential input voltage for high accu- racy applications. 10 90 100 0% 1v 1v figure 25. clipping behavior 15 0 20 3 0 6 9 12 16 12 8 4 supply voltage ?volts maximum output swing ? volts v p ? v n ? figure 26. maximum output swing vs. supply
AD830 rev. a C11C choice of polarity the sign of the gain is easily selected by choosing the polarity of the connections to the + and C inputs of the x g m stage. swap- ping between inverting and noninverting gain is possible simply by reversing the input connections. the response of the ampli- fier is identical in either connection, except for the sign change. the bandwidth, high impedance, transient behavior, etc., of the AD830, is symmetrical for both polarities of gain. this is very advantageous and unlike an op amp. input impedance the relatively high input impedance of the AD830, for a differ- ential receiver amplifier, permits connections to modest imped- ance sources without much loading or loss of common-mode rejection. the nominal input resistance is 300 k w . the real limit to the upper value of the source resistance is in its effect on common-mode rejection and bandwidth. if the source resistance is in only one input, then the low frequency common-mode re- jection will be lowered to ? r in /r s . the source resistance/input capacitance pole f = 1 2 p r s c in ? ? ? ? limits the bandwidth. furthermore, the high frequency common-mode rejection will be additionally lowered by the difference in the frequency re- sponse caused by the r s 3 c in pole. therefore, to maintain good low and high frequency common-mode rejection, it is rec- ommended that the source resistances of the + and C inputs be matched and of modest value ( 10 k w ). handling bias currents the bias currents are typically 4 m a flowing into each pin of the g m stages of the AD830. since all applications possess some fi- nite source resistance, the bias current through this resistor will create a voltage drop (i bias 3 r s ). the relatively high input im- pedance of the AD830 permits modest values of r s , typically 10 k w . if the source resistance is in only one terminal, then an objectional offset voltage may result (e.g., 4 m a 3 5 k w = 20 mv). placement of an equal value resistor in series with the other input will cancel the offset to first order. however, due to mismatches in the resistances, a residual offset will remain and likely be greater than bias current (offset current) mismatches. applying feedback the AD830 is intended for use with gain from 1 to 100. gains greater than one are simply set by a pair of resistors connected as shown in the difference amplifier (figure 35) with gain >1. the value of the bottom resistor r 2 , should be kept less than 1 k w to insure that the pole formed by c in and the parallel con- nection of r 1 and r 2 is sufficiently high in frequency so that it does not introduce excessive phase shift around the loop and de- stabilizes the amplifier. a compensating resistor, equal to the parallel combination of r 1 and r 2 , should be placed in series with the other y g m stage input to preserve the high frequency common-mode rejection and to lower the offset voltage induced by the input bias current. output common mode the output swing of the AD830 is defined by the differential in- put voltage, the gain and the output common. depending on the anticipated signal span, the output common (or ground) may be set anywhere between the allowable peak output voltage in a manner similar to that described for input voltage common mode. a plot of the peak output voltage versus supply is shown in figure 26. a prediction of the common-mode range versus the peak output differential voltage can be easily derived from the maximum output swing as v ocm = v max Cv peak . output current the absolute peak output current is set by the short circuit cur- rent limiting, typically greater that 60 ma. the maximum drive capability is rated at 50 ma, but without a guarantee of distor- tion performance. best distortion performance is obtained by keeping the output current 20 ma. attempting to drive large voltages into low valued resistances (e.g., 10 v into 150 w ) will cause an apparent lowering of the limit for output signal swing, but is just the current limiting behavior. driving cap loads the AD830 is capable of driving modest sized capacitive loads while maintaining its rated performance. several curves of band- width versus capacitive load are given in figures 15 and 18. the AD830 was designed primarily as a low distortion video speed amplifier, but with a tradeoff, giving up very large capacitive load driving capability. if very large capacitive loads must be driven, then the network shown in figure 27 should be used to insure stable operation. if the loss of gain caused by the resistor r s in series with the load is objectionable, then the optional feedback network shown may be added to restore the lost gain. 5 8 4 1 2 3 7 6 a=1 AD830 g m c g m + input signal +v s 0.1 m f r s 36.5 w v out r s c 1 100pf r 1 1k w r 1 0.1 m f ? s * optional feedback network z cm v cm figure 27. circuit for driving large capacitive loads 3 ?2 ?7 100k 100m 10m 1m 10k ? ? ? 0 ?4 ?1 ?8 ?5 closed-loop amplitude response ?db frequency ?hz 15v 5v figure 28. closed-loop response vs. frequency with 100 pf load and series resistor compensation
AD830 rev. a C12C supplies, bypassing and grounding (figure 29) the AD830 is capable of operating over a wide range of supply voltages, both single and dual supplies. the coupling may be dc or ac provided the input and output voltages stay within the specified common-mode voltage limits. for dual supplies, the device works from 4 v to 16.5 v. single supply operation is possible over +8 v to +33 v. it is also possible to operate the part with split supply voltages (e.g., +24 v, C5 v) for special applications such as level shifting. the primary constraint is that the total potential between the two supplies does not exceed 33 v. inclusion of power supply bypassing capacitors is necessary to achieve stable behavior and the specified performance. it is es- pecially important when driving low resistance loads. at a mini- mum, connect a 0.1 m f ceramic capacitor at the supply lead of the AD830 package. in addition, for the best by passing, we rec- ommend connecting a 0.01 m f ceramic capacitor and 4.7 m f tantalum capacitor to the supply lead going to the AD830. 0.1 m f load gnd lead v p and v n 0.01 m f 4.7 m f v p and v n load gnd lead (a) (b) figure 29. supply decoupling options the AD830 is designed by its functionality to be capable of rejecting noise and dissimilar potentials in the ground lines. therefore, proper care is necessary to realize the benefits of the differential amplification of the part. separation of the input and output grounds is crucial in rejection of the common mode noise at the inputs and eliminating any ground drops on the in- put signal line. for example, connecting the ground of a coaxial cable to the AD830 output common (board ground) could de- grade the cmr and also introduce power-down loading on cable grounds. however, it is also necessary as in any electronic system, to provide a return path for bias currents back to their original power supply. this is accomplished by providing a con- nection between the differing grounds through a modest imped- ance labeled z cm (e.g., 100 w ). single supply operation the AD830 is capable of operating in single power supply appli- cations down to a voltage of +8 v, with the generalized connec- tion shown in figure 30. there is a constraint on the common-mode voltage at the input and output which estab- lishes the range for these voltages. direct coupling may be used for input and output voltages which lie in these ranges. any gain network applied needs to be referred to the output common connection or have an appropriate offset voltage. in situations where the signal lies at a common voltage outside the common mode range of the AD830 direct coupling will not work, so ac coupling should be used. a tested application included later in this data sheet (figure 42), shows how to easily accomplish cou- pling to the AD830. for single supply operation where direct coupling is desired the input and output common-mode curves (figures 31 and 32) should be used. 5 8 4 1 2 3 7 6 a=1 AD830 g m c + v p + + v out v ocm v icm v in v out = (v in ?v icm ) + v ocm g m figure 30. general single supply connection 30 0 2.0 4 0 12 16 24 1.6 1.2 0.8 0.4 differential input voltage ?v peak common mode voltage limits ? volts 8 28 20 v p = +30v v p = +15v v p = +10v to gnd figure 31. input common-mode range for single supply 0 30 4 10 12 16 24 26 22 18 14 supply voltage ?volts maximum output swing ? volts 8 28 20 to v p to gnd figure 32. output swing limit for single supply
AD830 rev. a C13C differential line receiver the AD830 was specifically designed to perform as a differen- tial line receiver. the circuit in figure 33 shows how simple it is to configure the AD830 for this function. the signal from sys- tem a is received differentially relative to as common, and that voltage is exactly reproduced relative to the common in sys- tem b. the common-mode rejection versus frequency, shown in figure 1, is excellent, typically 100 db at low frequencies. the high input impedance permits the AD830 to operate as a bridg- ing amplifier across low impedance terminations with negligible loading. the differential gain and phase specifications are very good as shown in figure 7 for 500 w and figure 10 for 150 w . the input and output common should be separated to achieve the full cmr performance of the AD830 as a differential ampli- fier. however, a common return path is necessary between sys- tems a and b. 45 36 AD830 1 2 8 7 a=1 common in system b v out = v 1 ?v 2 common in system a v 1 v 2 input signal v cm z cm v p 0.1? v out v n 0.1? g m g m c figure 33. differential line receiver wide range level shifter the wide common-mode range and accuracy of the AD830 al- lows easy level shifting of differential signals referred to an input common-mode voltage to any new voltage defined at the out- put. the inputs may be referenced to levels as high as 10 v at the inputs with a 2 v swing about 10 v. in the circuit of fig- ure 34, the output voltage, v out , is defined by the simple equa- tion shown below. the excellent linearity and low distortion are preserved over the full input and output common-mode range. the voltage sources need not be of low impedance, since the high input resistance and modest input bias current of the AD830 v-to-i converters permit the use of resistive voltage di- viders as reference voltages. 45 3 6 AD830 1 2 8 7 a=1 output common v out = v 1 ?v 2 + v 3 v p 0.1? v out v n 0.1? g m g m input common v 3 c v 1 v 2 input signal figure 34. differential amplification with level shifting difference amplifier with gain > 1 the AD830 can provide instrumentation amplifier style differ- ential amplification at gains greater than 1. the input signal is connected differentially and the gain is set via feedback resistors as shown in figure 35. the gain, g = (r 2 + r 1 )/r 2 . the AD830 can provide either inverting or noninverting differential amplifi- cation. the polarity of the gain is established by the polarity of the connection at the input. feedback resistors r 2 should gener- ally be r 2 1 k w to maintain closed-loop stability and also keep bias current induced offsets low. highest cmrr and lowest dc offsets are preserved by including a compensating resistor in series with pin 3. the gain may be as high as 100. 4 5 36 AD830 1 2 8 7 a=1 v out = (v 1 ?v 2 ) (1+r 1 /r 2 ) v p 0.1? v out v n 0.1? g m g m r1 r2 z cm r 1 r 2 v 1 v 2 input signal c v cm figure 35. gain of g differential amplifier, g > 1 offsetting the output with gain some applications, such as a/d drivers, require that the signal be amplified and also offset, typically to accommodate the input range of the device. the AD830 can offset the output signal very simply through pin 3 even with gain > 1. the voltage ap- plied to pin 3 must be attenuated by an appropriate factor so that v 3 3 g = desired offset. in figure 36, a resistive divider from a voltage reference is used to produce the attenuated offset voltage. 45 3 6 AD830 1 2 8 7 a=1 v out = (v 1 ?v 2 ) (1+r 1 /r 2 ) v 1 v 2 input signal v p 0.1? v out v n 0.1? g m g m r 3 r 4 z cm r 2 r 1 r 1 r 2 v 3 v ref c v cm figure 36. offsetting the output with differential gain > 1
AD830 rev. a C14C loop through or line bridging amplifier (figure 37) the AD830 is ideally suited for use as a video line bridging am- plifier. the video signal is tapped from the conductor of the cable relative to its shield. the high input impedance of the AD830 provides negligible loading on the cable. more signifi- cantly, the benign loading is maintained while the AD830 is powered-down. coupled with its good video load driving per- formance, the AD830 is well suited to video cable monitoring applications. 45 36 AD830 1 2 8 7 a=1 v p 0.1? v out v n 0.1? g m g m r g 75 w 75 w 499 w 499 w optional c c 249 w c figure 37. cable tap amplifier resistorless summing direct, two input, resistorless summing is easily realized from the general unity gain mode. by grounding v x2 and applying the two inputs to v x1 and v y1 , the output is the exact sum of the applied voltages v 1 and v 3 , relative to common; v out = v 1 + v 3 . a diagram of this simple, but potent application is shown below in figure 38. the AD830 summing circuit possesses sev- eral virtues not present in the classic op amp based summing circuits. it has high impedance inputs, no resistors, very precise summing, high reverse isolation and noninverting gain. achiev- ing this function and performance with op amps requires signifi- cantly more components. 45 36 AD830 1 2 8 7 a=1 v out = v 1 + v 3 v p out v n g m g m v 1 v 3 c figure 38. resistorless summing amplifier 2 3 gain bandwidth line driver a gain of two, without the use of resistors, is possible with the AD830. this is accomplished by grounding v x2 , tying the two inputs v x1 and v y1 together and applying the input, v in , to this wired connection. the output is exactly twice the applied volt- age, v in ; v out = 2 3 v in . figure 39 below shows the connec- tions for this highly useful application. the most notable characteristic of this alternative gain of two is that there is no loss of bandwidth as in a voltage feedback op amp based gain of +2 where the bandwidth is halved, therefore, the gain band- width is doubled. also, this circuit is accurate without the need for any precise valued resistors, as in the op amp equivalents, and it possess excellent differential gain and phase performance as shown in figures 40 and 41. 45 36 AD830 1 2 8 7 a=1 v p 0.1? v out v n 0.1? g m g m 75 w 75 w v in c figure 39. full bandwidth line driver (g = +2) supply voltage ? volts .10 15 .03 .01 6 .02 5 .06 .04 .05 .07 .08 .09 14 13 12 11 10 9 8 7 differential gain ?% differential phase ?degrees .20 .06 .02 .04 .12 .08 .10 .14 .16 .18 phase gain gain = +2 r l = 150 w freq = 3.58mhz 0 to 0.7v figure 40. differential gain and phase for the circuit of figure 39 0.2 ?.3 ?.8 100k 100m 10m 1m 10k ?.2 ?.1 0 0.1 ?.7 ?.6 ?.5 ?.4 frequency ?hz amplitude response ?db v s = 15v v s = 10v v s = 5v r l = 150 w gain = +2 figure 41. 0.1 db gain flatness for the circuit of figure 39
AD830 rev. a C15C ac coupled line receiver the AD830 is configurable as an ac coupled differential ampli- fier on a single or bipolar supply voltages. all that is needed is inclusion of a few noncritical passive components as illustrated below in figure 42. a simple resistive network at the x g m input establishes a common-mode bias. here, the common mode is centered at 6 volts, but in principle can be any voltage within the common-mode limits of the AD830. the 10 k w re- sistors to each input bias the x g m stage with sufficiently high impedance to keep the input coupling corner frequency low, but not too large so that residual bias current induced offset voltage becomes troublesome. for dual supply operation, the 10 k w resistors may go directly to ground. the output common is con- veniently set by a zener diode for a low impedance reference to preserve the high frequency cmr. however, a simple resistive divider will work fine and good high frequency cmr can be maintained by placing a compensating resistor in series with the +y input. the excellent cmrr response of the circuit is shown in figure 43. a plot of the 0.1 db flatness from 10 hz is also shown. with the use of 10 m f capacitors, the cmr is >90 db down to a few tens of hertz. this level of performance is almost impossible to achieve with discrete solutions. 4 5 3 6 AD830 1 2 8 7 a=1 z cm +12v 0.1? v out g m g m 75 w 75 w 1000? 75 w coax cable +12v 4.7k w 6.8v 1n4736 +v s 10k w 10k w 10? 10? r t 10k w 10k w 2k w * *optional tuning for improving very low frequency cmr. c input signal figure 42. ac coupled line receiver 120 100 20 10 100 100m 10m 1m 100k 10k 1k 80 60 40 frequency ?hz common-mode rejection ?db with circuit trimmed using external 2k w potentiometer without external 2k w potentiometer figure 43. common-mode rejection vs. frequency for line receiver 1 ?.4 ?.9 10 100 10m 1m 100k 10k 1k ?.3 ?.2 ?.1 0 ?.8 ?.7 ?.6 ?.5 amplitude response db frequency ?hz figure 44. amplitude response vs. frequency for line receiver
AD830 rev. a C16C outline dimensions dimensions shown in inches and (mm). cerdip (q) package 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 15 0 0.005 (0.13) min 0.055 (1.4) max 1 pin 1 4 5 8 0.310 (7.87) 0.220 (5.59) 0.405 (10.29) max 0.200 (5.08) max seating plane 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) bsc plastic mini-dip (n) package pin 1 0.280 (7.11) 0.240 (6.10) 4 5 8 1 seating plane 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) min 0.210 (5.33) max 0.160 (4.06) 0.115 (2.93) 0.430 (10.92) 0.348 (8.84) 0.022 (0.558) 0.014 (0.356) 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 8-pin soic (r) package 1 4 5 8 0.050 (1.27) typ 0.188 (4.75) 0.198 (5.00) 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.200) 0.014 (0.36) 0.018 (0.46) 0.181 (4.60) 0.205 (5.20) 0.102 (2.59) 0.094 (2.39) 0.020 (0.50) 0.045 (1.15) 0.007 (0.18) 0.015 (0.38) 0.004 (0.10) 0.010 (0.25) c1735C24C10/92 printed in u.s.a. all brand or product names mentioned are trademarks or registered trademarks of their respective holders.

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